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HI-506A, HI-507A, HI-508A, HI-509A
Data Sheet October 30, 2007 FN3143.6
16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection
The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-channel multiplexer, the HI-507A is an 8-channel differential multiplexer, the HI-508A is a single 8-channel multiplexer and the HI-509A is a differential 4-channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Note AN520.
Features
* Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P * No Channel Interaction During Overvoltage * Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V * Fail Safe with Power Loss (No Latch-Up) * Break-Before-Make Switching * Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V * Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns * Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW * Pb-Free Available (RoHS Compliant)
Applications
* Data Acquisition Systems * Industrial Controls * Telemetry
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved
HI-506A, HI-507A, HI-508A, HI-509A Ordering Information
PART NUMBER HI1-0506A-2 HI1-0506A-5 HI1-0506A-8 HI3-0506A-5 HI3-0506A-5Z (Note 1) HI3-0507A-5 HI3-0507A-5Z (Note 1) HI1-0508A-8 HI3-0508A-5 HI3-0508A-5Z (Note 1) HI1-0509A-2 HI1-0509A-5 HI1-0509A-8 HI3-0509A-5 HI3-0509A-5Z (Note 1) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. PART MARKING HI1-506A-2 HI1-506A-5 HI1-506A-8 HI3-506A-5 HI3-506A-5Z HI3-507A-5 HI3-507A-5Z HI1-508A-8 HI3-508A-5 HI3-508A-5Z HI1-509A-2 HI1-509A-5 HI1-509A-8 HI3-509A-5 HI3-509A-5Z TEMP. RANGE (C) -55 to +125 0 to +75 -55 to +125 + 160 Hour Burn-In 0 to +75 0 to +75 0 to +75 0 to +75 -55 to +125 + 160 Hour Burn-In 0 to +75 0 to +75 -55 to +125 0 to +75 -55 to +125 + 160 Hour Burn-In 0 to +75 0 to +75 PACKAGE 28 Ld CERDIP 28 Ld CERDIP 28 Ld CERDIP 28 Ld PDIP 28 Ld PDIP (Note 2) (Pb-free) 28 Ld PDIP 28 Ld PDIP (Note 2) (Pb-free) 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP (Note 2) (Pb-free) 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP (Note 2) (Pb-free) PKG. DWG. # F28.6 F28.6 F28.6 E28.6 E28.6 E28.6 E28.6 F16.3 E16.3 E16.3 F16.3 F16.3 F16.3 E16.3 E16.3
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Pinouts
HI-506A (CERDIP, PDIP) TOP VIEW
+VSUPPLY 1 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 VREF 13 ADDRESS A3 14 28 OUT 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2 +VSUPPLY 1 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 VREF 13 NC 14
HI-507A (PDIP) TOP VIEW
28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2
HI-508A (CERDIP, PDIP) TOP VIEW
A0 1 ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8
HI-509A (CERDIP, PDIP) TOP VIEW
A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Truth Tables
HI-506A A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H "ON" CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A1 X L L H H A0 X L H L H HI-509A EN L H H H H "ON" CHANNEL PAIR None 1 2 3 4 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H HI-508A EN L H H H H H H H H "ON" CHANNEL None 1 2 3 4 5 6 7 8
HI-507A A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H "ON" CHANNEL PAIR None 1 2 3 4 5 6 7 8
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Functional Diagrams
HI-506A
1k
HI-507A
OUT A
IN 1 IN 2
1k 1k
OUT
IN 1A
IN 8A DECODER/ DRIVER 1k IN 1B
1k 1k OUT B
IN 16 IN 8B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT
1k
DECODER/ DRIVER
DIGITAL INPUT
PROTECTION VREF A0 A1 A2 A3 EN
OVERVOLTAGE CLAMP AND SIGNAL ISOLATION
5V REF
LEVEL SHIFT
DIGITAL INPUT
PROTECTION VREF A0
A1
A2
EN
HI-508A
1k
HI-509A
OUT A
IN 1 IN 2
1k 1k
OUT
IN 1A
IN 4A DECODER/ DRIVER 1k IN 1B
1k 1k OUT B
IN 8 IN 4B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT
1k
DECODER/ DRIVER
DIGITAL INPUT
PROTECTION A0
A1
A2
EN
OVERVOLTAGE CLAMP AND SIGNAL ISOLATION
5V REF
LEVEL SHIFT
DIGITAL INPUT
PROTECTION A0
A1
EN
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE CIRCUIT V+
R10 R9 VREF Q1 Q4 D3 GND LEVEL SHIFTER V+ P P P P P P P P P
OVERVOLTAGE PROTECTION V+ D2
P
N
R2 R5 R3 N N R4 R6 N N N N R8 N N R7
LEVEL SHIFTED ADDRESS TO DECODE
R1 200
D1
N GND V-
VADD IN
ADDRESS DECODER
V+
P
P
P
P
P
P
P
N A0 OR A0 A1 OR A1 A2 OR A2 A3 OR A3
N
N
TO P-CHANNEL DEVICE OF THE SWITCH
N
N
TO N-CHANNEL DEVICE OF THE SWITCH
N
N
ENABLE DELETE A3 OR A3 INPUT FOR HI-507A, HI-508A, HI-509A DELETE A2 OR A2 INPUT FOR HI-509A
V-
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams
(Continued) MULTIPLEX SWITCH
FROM DECODE OVERVOLTAGE PROTECTION N
V+ P Q5
R11 1k IN
D6
D7
D4
D5
N OUT
N Q6
VP FROM DECODE
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . (V-) -20V to (V+) +20V Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max) . . 40mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) JC (C/W) 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 16 Ld CERDIP Package. . . . . . . . . . . . 75 22 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Ranges HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . .-55C to +125C HI-506A/507A/508A/509A-5. . . . . . . . . . . . . . . . . . . 0C to +75C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. -2, -8 -5
PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA
TEST CONDITIONS
TEMP (C)
MIN MAX MIN MAX (Note 12) TYP (Note 12) (Note 12) TYP (Note 12) UNITS
Note 4
25 Full
25 -
0.5 80 300 300 -
1.0 500 1000 500 1000
25 -
0.5 80 300 300 -
1.0 1000 1000
s s ns ns ns ns ns s s s s dB pF
Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN)
Note 4 Note 4
25 25 Full
Enable Delay (OFF), tOFF(EN)
Note 4
25 Full
Settling Time, tS HI-506A and HI-507A To 0.1% To 0.01% HI-508A and HI-509A To 0.1% To 0.01% Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) HI-506A HI-507A HI-508A HI-509A Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL Input High Threshold, VAH (Note 11) Note 4 Note 4 Full Full 4.0 0.8 4.0 0.8 V V 25 25 25 25 25 25 52 30 25 12 10 0.1 52 30 25 12 10 0.1 pF pF pF pF pF pF Note 9 25 25 25 25 25 25 1.2 3.5 1.2 3.5 68 10 1.2 3.5 1.2 3.5 68 10 -
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued) -2, -8 PARAMETER Input Leakage Current (High or Low), IA MOS Drive, VAL , HI-506A/HI-507A MOS Drive, VAH , HI-506A/HI-507A ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Note 4 Notes 4, 5 Full 25 Full Off Input Leakage Current, IS(OFF) Notes 4, 6 25 Full Off Output Leakage Current, ID(OFF) HI-506A HI-507A HI-508A HI-509A ID(OFF) With Input Overvoltage Applied Note 7 Notes 4, 6 25 Full Full Full Full 25 Full On Channel Leakage Current, ID(ON) HI-506A HI-507A HI-508A HI-509A Differential Off Output Leakage Current, IDIFF, (HI-507A, HI-509A Only) POWER SUPPLY CHARACTERISTICS Current, I+ Current, IPower Dissipation, PD NOTES: 4. 100% tested for Dash 8. Leakage currents not tested at -55C. 5. VOUT = 10V, IOUT = +100A. 6. 10nA is the practical lower limit for high speed measurement in the production test environment. 7. Analog Overvoltage = 33V. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25C. 9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 100kHz. 10. VEN , VA = 0V or 4V. 11. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended. 12. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. Notes 4, 10 Notes 4, 10 Full Full Full 0.5 0.02 7.5 2.0 1.0 0.5 0.02 7.5 2.0 1.0 mA mA mW Notes 4, 6 25 Full Full Full Full Full -15 1.2 1.5 0.03 0.1 4.0 0.1 +15 1.5 1.8 50 300 200 200 100 2.0 300 200 200 100 50 -15 1.5 1.8 0.03 0.1 4.0 0.1 +15 1.8 2.0 50 300 200 200 100 300 200 200 100 50 V k k nA nA nA nA nA nA nA nA A nA nA nA nA nA nA TEST CONDITIONS Notes 4, 8 VREF = +10V VREF = +10V TEMP (C) Full 25 25 -5
MIN MAX MIN MAX (Note 12) TYP (Note 12) (Note 12) TYP (Note 12) UNITS 6.0 1.0 0.8 6.0 1.0 0.8 A V V
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = +25C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified
100A
V2
IN
OUT V2 100A
VIN
rON =
FIGURE 1A. TEST CIRCUIT
1.4 +125C NORMALIZED RESISTANCE (REFERRED TO VALUE AT 15V) 1.3 ON RESISTANCE (k) 1.2 1.1 +25C 1.0 0.9 0.8 0.7 0.6 -10 -55C 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) -55C TO +125C VIN = +5V
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 1. ON RESISTANCE
100nA
10nA LEAKAGE CURRENT OFF OUTPUT CURRENT ID(OFF) EN OUT A ID(OFF) +0.8V
ON LEAKAGE CURRENT ID(ON) 1nA
100pA
OFF INPUT LEAKAGE CURRENT IS(OFF)
10pA
25
50
75
100
125
TEMPERATURE (C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 13)
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FN3143.6 October 30, 2007
10V
10V
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = +25C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
OUT A IS(OFF) EN 10V +0.8V A0 A1 EN
OUT A ID(ON)
10V
FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 13) NOTE:
13. Two measurements per channel: 10V and +10V. (Two measurements per device for ID(OFF) 10V and +10V.) FIGURE 2. LEAKAGE CURRENTS
18 ANALOG INPUT CURRENT (mA) 15 12 9 6 3 0 15 18 21 24 27 30 33 36 ANALOG INPUT OVERVOLTAGE (V) OUTPUT OFF LEAKAGE CURRENT ID(OFF) ANALOG INPUT CURRENT (IIN)
6 5 4 3 2 1 0
OUTPUT OFF LEAKAGE CURRENT (nA)
FIGURE 3A. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
14 -55C 12 SWITCH CURRENT (mA) 10 +125C 8 6 4 2 0 0 2 4 6 8 10 12 14 VOLTAGE ACROSS SWITCH (V) VIN A +25C
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. ON CHANNEL CURRENT
10V
10V 4V
FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 13)
7
A
IIN
A
ID(OFF)
VIN
FIGURE 3B. TEST CIRCUIT
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
FIGURE 4B. TEST CIRCUIT
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
8 A
TA = +25C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
+15V/+10V +ISUPPLY
SUPPLY CURRENT (mA)
6 A3 VSUPPLY = 15V VA VSUPPLY = 10V 2 +4V 50 A2 A1 A0 EN GND 0 1k 10k 100k TOGGLE FREQUENCY (Hz) 1M 10M
V+ IN 1 HI-506A IN 2 THRU IN 7/IN 15 10V/ IN 8/IN 16 OUT V5V 10V/5V
4
10 M
14 pF
A -ISUPPLY -15V/-10V
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY
Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 5B. TEST CIRCUIT
FIGURE 5. DYNAMIC SUPPLY CURRENT
900 800 ACCESS TIME (ns) 700 600 500 +4V 400 300 3 4 5 6 7 8 9 10 11 12 LOGIC LEVEL (HIGH) (V) 13 14 15 VA 50 VREF = OPEN FOR LOGIC HIGH LEVEL 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V A3 A2 A1 A0 EN GND VREF
+15V
V+ IN 1
10V
IN 2 THRU IN 7/IN 15 HI-506A IN 16 OUT V10V
10 k
50 pF
-15V
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)
Similar connection for HI-507A/HI-580A/HI-509A
FIGURE 6B. TEST CIRCUIT
VAH = 4.0V
1/ V 2 AH
ADDRESS DRIVE (VA) 0V
VA INPUT 2V/DIV. S1 ON
+10V OUTPUT 10% tA
OUTPUT 5V/DIV.
-10V
S16 ON 200ns/DIV.
FIGURE 6C. MEASUREMENT POINTS FIGURE 6. ACCESS TIME
FIGURE 6D. WAVEFORMS
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
A3 A2 HI-506A IN 1 IN 2 THRU VA 50 A1 A0 +4.0V EN GND IN 7/IN 15 IN 8/IN 16 OUT 1k 50pF 50% 50% VOUT 0V ADDRESS DRIVE (VA)
TA = +25C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
+5V VAH = 4.0V
OUTPUT
Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 7A. TEST CIRCUIT
tOPEN
FIGURE 7B. MEASUREMENT POINTS
VA INPUT 2V/DIV.
S1 ON
S16 ON
OUTPUT 0.5V/DIV.
100ns/DIV.
FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
A3 A2 HI-506A IN 1 IN 2 THRU IN 7/IN 15 IN 8 /IN 16 +10V VAH = 4.0V 50% 50% ENABLE DRIVE (VA) 0V A0 EN VA 50 GND OUT 1k VOUT 50pF 90% OUTPUT 10% 0V tON(EN)
TA = +25C, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
A1
Similar connection for HI-507A//HI-508A/HI-509A
FIGURE 8A. TEST CIRCUIT
tOFF(EN)
FIGURE 8B. MEASUREMENT POINTS
ENABLE DRIVE 2V/DIV.
DISABLED
ENABLED (S1 ON)
OUTPUT 2V/DIV.
100ns/DIV.
FIGURE 8C. WAVEFORMS FIGURE 8. ENABLE DELAYS
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics
DIE DIMENSIONS: 159 mils x 83.9 mils METALLIZATION: Type: CuAl Thickness: 16kA 2kA SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI
Metallization Mask Layouts
HI-506A
EN (18) A0 (17) A1 A2 (16) (15) A3 VREF (14) (13) GND (12) EN (18) A0 (17)
HI-507A
A1 A2 (16) (15) NC VREF (14) (13) GND (12)
IN 1 (19) IN 2 (20)
IN 9 (11) IN 10 (10)
IN 1A (19) IN 2A (20)
IN 1B (11) IN 2B (10)
IN 3 (21) IN 4 (22)
IN 11 (9) IN 12 (8)
IN 3A (21) IN 4A (22)
IN 3B (9) IN 4B (8)
IN 5 (23) IN 6 (24)
IN 13 (7) IN 14 (6)
IN 5A (23) IN 6A (24)
IN 5B (7) IN 6B (6)
IN 7 (25) IN 8 (26)
IN 15 (5) IN 16 (4)
IN 7A (25) IN 8A (26)
IN 7B (5) IN 8B (4)
V- (27)
OUT (28)
+V (1)
NC (2)
V- (27)
OUT A (28)
+V (1)
OUT B(2)
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics
DIE DIMENSIONS: 108 mils x 83 mils METALLIZATION: Type: CuAl Thickness: 16kA 2kA SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 253 PROCESS: CMOS-DI
Metallization Mask Layouts
HI-508A HI-509A
IN 6 (11)
IN 7 IN 8 (10) (9)
OUT (8)
IN 4 IN 3 (7) (6)
IN 3B IN 4B OUT B (11) (10) (9)
OUT A (8)
IN 4A IN 3A (7) (6)
IN 5 (12) +V (13) GND (14)
IN 2 (5) IN 1 (4) -V (3)
IN 2B (12) IN 1B (13) +V (14)
IN 2A (5) IN 1A (4) -V (3)
A2 (15)
A1 (16)
A0 (1)
EN (2)
GND (15)
A1 (16)
A0 (1)
EN (2)
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FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
17
FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
18
FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
19
FN3143.6 October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E
A A1 A2 B B1 C D D1 E E1 e eA eB L N
e
eA eC
C
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN3143.6 October 30, 2007

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